A single event effect (SEE) is a short-term confined ionization effect in which a single particle interacts with the semiconductor material, causing the generation of excess free-carriers along the entirety of its path through the material. Single event effects may manifest themselves as single event upsets (SEU) or single event transients (SET). An SEU refers to the single-event induced corruption of a logic state in a storage element. An SET refers to a single-event induced, transient voltage signal at the node of a combinational logic element that competes with other legitimate data signals. An SET can lead to an SEU if the SET propagates to the input of a storage element and is latched. If an SEU is read by the system, the result is a soft error.
In digital integrated circuit design, sequential digital systems are typically structured such that data are clocked from the output of one storage element through combinational logic to the input of the next storage element. Single event transients generated in combinational logic are a major, often dominant, contributor to soft errors in integrated circuits. The radiation-hardened-by-design (RHBD) community has put forth much effort to address the problem of SETs, and numerous techniques have been developed to mitigate the effect of SETs. SET utilization techniques can generally be grouped into two categories: temporal mitigation and spatial mitigation. Temporal mitigation techniques involve a direct tradeoff between circuit speed and hardness since hardness is gained by inserting circuit delays proportional to the duration of the SET to be mitigated. Spatially redundant techniques circumvent the speed penalty of temporal techniques by triplicating the logic and using majority voting circuitry. However, spatially redundant techniques induce significant area and power penalties.
One method of dealing with SEUs in storage elements has been to use Dual Interlocked Storage CEII (DICE) latches. A conventional DICE latch schematic is shown in FIG. 1, where the feedback paths are interlocked to mitigate single-node upset susceptibility. The DICE latch immunity to single-node upsets is due to distributed logic storage across four separate circuit nodes and the restoring property of redundant, interlocked feedback loops. Although the DICE latch is robust to direct corruption by a single event, it is still vulnerable to SETs arriving at its data input terminal. For example, as noted by Blum and Delgado-Frias in “Schemes for Eliminating Transient-Width Clock Overhead From SET-Tolerant Memory-Based Systems,” IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 3, June 2006, DICE latches can only be used to provide hardened data transfer systems without combinational logic. In order to form a sequential digital system for purposes other than data transfer, combinational logic must be incorporated between the DICE latches, thus rendering the system vulnerable to SETs.
Hardened combinational logic is vital to designing a sequential system that is robust against single events. One way to demonstrate that combination logic is hardened against SETs is to show that an SET is not capable of propagating past subsequent combinational logic gates. For example, it has been demonstrated that traditional cascode voltage switched logic (CVSL) NAND gates do not propagate an SET that results in a 010 transition, however an SET resulting in a 101 transition is capable of propagating. The schematic of a generic CVSL gate, where the gate is comprised of a cross-coupled PMOS pair driven by complementary NMOS logic trees capable of implementing any boolean function, is shown in FIG. 2. The CVSL family is a differential logic family in that it requires both a true and complement input, and produces both a true and complement output. The cross-coupled PMOS pair in CVSL has the potential to be hardened via interlocked feedback. However, while CVSL gates have an increased tolerance to SETs compared to standard CMOS gate, they are still capable of propagating SETs in some cases. In particular, the generation and propagation of an SET in CVSL gates will be highly dependent on both the SET pulse width and the ratio of drive strengths between the PMOS half latch and the NMOS logic tree. Due to the dependence on SET pulse width and drive strength, the hardness of a CVSL gate is extremely dependent on transistor sizing, technology selection and environment setting. These dependencies require designers to fully characterize the radiation response of a technology in order to ensure hardness.